Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell

Abstract

The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon-based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET-based SRAM circuit is designed using the look up table-based Verilog A code obtained from TCAD values of the device. After verifying SRAM circuit for its functionality, the stability parameters, read static noise margin (RSNM), write static noise margin (WSNM), read/write delay, and power consumption are evaluated. It is observed that the circuit has a good stability of noise margin and lesser delay. The radiation study is carried out using a transient current source striking at one of the output nodes. This causes single event upset (SEU) which changes the data stored in the memory cell giving rise to soft error (SER). SER is recovered by the radiation hardening by design (RHBD) technique with an additional RC network between two cross coupled inverters. The performance metrics, read/write delay, and the power consumption before, during, and after the radiation strike are analyzed. It is observed that SER gets totally eliminated with less recovery time at the expense of a slight increase in power and delay.