Highly-Sensitive Integrating Optical Receiver With Large PIN Photodiode

Abstract

This paper presents a highly-sensitive monolithic optoelectronic receiver in $\mathbf{180\, {nm}}$ CMOS. An integrating front-end with noise matching via an negative Miller capacitance is proposed, to reduce the power penalty imposed by large PIN photodiodes (PDs). Three new multi-dot PIN PDs are integrated with the front-end. At a wavelength of $\mathbf{642\, {nm}}$ and reverse bias of $\mathbf {8}\,\mathbf {V}$, their responsivity (capacitance) is $\mathbf {0.38\, {A/W}}$ ($\mathbf{29\, {fF}}$), $\mathbf {0.36\, {A/W}}$ ($\mathbf{33\, {fF}}$), and $\mathbf {0.43\, {A/W}}$ ($\mathbf{123\, {fF}}$), respectively. Compared to our previous integrating PIN receivers, the light-sensitive area is up to 30 times larger. At a supply voltage of $\mathbf {1.8\, {V}}$, wavelength of $\mathbf{642\, {nm}}$, bit rate of $\mathbf {20\, {Mbit/s}}$, and reference ${\mathbf{BER}=2\cdot 10^{-3}}$, the prototype receiver achieves a sensitivity of $\mathbf {-55.4\, {dBm}}$ for the first PD, $\mathbf {-56.5\, {dBm}}$ for the second PD, and $\mathbf {-53.4\, {dBm}}$ for the third PD. The best sensitivity equals a distance of only $\mathbf {21.2\, {dB}}$ to the quantum limit.

Keywords

• CMOS
• capacitive feedback
• transimpedance amplifier
• noise matching
• negative capacitance
• p-i-n photodiode