An ASIC Implementation: Wave-Pipelined Circuit for Dual-Tree Complex Wavelet Transformation

Abstract

In digital systems, the wave-pipelining concepts are used to achieve maximal rate of operation. A high operating frequency are obtained by adjusting the two factors called clock skew, & clock period in order to latch the combinational logic circuit output as stable. In literature, only trial & error, manual procedures are used for the choice of the optimum clock period and clock skew values between input/outputs register of wave-pipelined circuit.The major contribution of this paper is to propose automated ASIC implementation using wave-pipelined circuits.to verify the proposal a dual-tree complex wavelet transformation algorithm is taken into consideration in which scheme is again carried out into 3 types i.e., Pipelining, wave-pipelining, non-pipeliningWith the implementation result survey, it is observed that wave -pipelined circuits are 30% more faster than that of non-pipelining circuits, pipelined circuits are 49% more faster than that of wave-pipelined circuits but occupies 30% more area and 3% more power dissipating than that of wave-pipelined circuits.