The influence of yield model parameters on the probability of defect occurrence

Abstract

This paper describes the analysis of the influence of yield loss model parameters on the calculation of the probability of arising shorts between conducting paths in IC’s. The characterization of the standard cell in AMS 0.8 μm CMOS technology is presented as well as obtained probability results and estimations of yield loss by changing values of model parameters.

Keywords

• yield model parameters
• spot defect
• probability of defect occurrence
• critical area