Some issues of automation of test program generation for branch units of microprocessors

Abstract

In this work, some issues of automated construction of test programs intended for functional verification of branch units of microprocessors are considered. Problems appearing when creating such programs are defined, and techniques for their automated solution are suggested. The article focuses on the general issues of branch processing mechanisms and does not touch upon the problems specific for concrete microprocessor architectures. The suggested techniques can be used in industrial test program generators.

Keywords

• <i>автоматизированное построение тестовых программ</i>
• <i>функциональная верификации модулей обработки переходов микропроцессоров</i>