An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

Yuet Ho Woo; Jianxin Yang; Junwen Li; Jianping Guo; Yanqi Zheng; Ka Nang Leung

doi:10.1109/ACCESS.2022.3178812

IEEE Access (Jan 2022)

An Analog-Assisted Digital LDO With Dynamic-Biasing Asynchronous Comparator

Yuet Ho Woo,
Jianxin Yang,
Junwen Li,
Jianping Guo,
Yanqi Zheng,
Ka Nang Leung

Affiliations

Yuet Ho Woo: Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, China
Jianxin Yang: School of Microelectronics, South China University of Technology, Guangzhou, China
Junwen Li: Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, China
Jianping Guo: ORCiD; School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China
Yanqi Zheng: ORCiD; School of Microelectronics, South China University of Technology, Guangzhou, China
Ka Nang Leung: ORCiD; Department of Electronic Engineering, The Chinese University of Hong Kong, Hong Kong, China

DOI: https://doi.org/10.1109/ACCESS.2022.3178812
Journal volume & issue: Vol. 10
pp. 56996 – 57002

Abstract

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This paper presents a digital low-dropout regulator (DLDO) with three-level switching (TLS) and analog-assisted (AA) structure formed by dynamic-biasing asynchronous comparator, capacitive-coupling RC network and auxiliary power switch. The proposed AA-DLDO is fabricated in a 65-nm CMOS process. The minimum load current is 18 $\mu \text{A}$ . The maximum undershoot is 200 mV under load transient of 4.82-mA/1-ns. The recovery time is 8 ns. The figure-of-merit of proposed design is better than the other DLDOs by more than 14 times.

Published in IEEE Access

ISSN: 2169-3536 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639

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