Peak-Power Aware Life-Time Reliability Improvement in Fault-Tolerant Mixed-Criticality Systems

Abstract

Mixed-Criticality Systems (MCSs) include tasks with multiple levels of criticality and different modes of operation. These systems bring benefits such as energy and resource saving while ensuring safe operation. However, management of available resources in order to achieve high utilization, low power consumption, and required reliability level is challenging in MCSs. In many cases, there is a trade-off between these goals. For instance, although using fault-tolerance techniques, such as replication, leads to improving the timing reliability, it increases power consumption and can threaten life-time reliability. In this work, we introduce an approach named ${\mathbf {L}}ife-time \,\,{\mathbf {P}}eak \,\,{\mathbf {P}}{ower~management~in}\,\,{\mathbf {M}}{ixed}-{\mathbf {C}}{riticality\,\, systems}$ (LPP-MC) to guarantee reliability, along with peak power reduction. This approach maps the tasks using a novel metric called Reliability-Power Metric (RPM). The LPP-MC approach uses this metric to balance the power consumption of different processor cores and to improve the life-time of a chip. Moreover, to guarantee the timing reliability of MCSs, a fault-tolerance technique, called task re-execution, is utilized in this approach. We evaluate the proposed approach by a real avionics task set, and various synthetic task sets. The experimental results show that the proposed approach mitigates the aging rate and reduces peak power by up to 20.6% and 17.6%, respectively, compared to state-of-the-art.

Keywords

• Mixed-critically embedded systems
• life-time reliability
• peak power management
• fault-tolerance
• multi-core processor