Inductance Model of a Backside Integrated Power Inductor in 2.5D/3D Integration

Abstract

Inductor integration is of vital importance for miniaturization of power supply on chips. In this paper, a backside integrated power inductor is presented. The inductor is placed at the backside of a silicon interposer and connected to the front side metal layers by through-silicon vias (TSVs) for area saving and simple fabrication. An inductance model is proposed to effectively capture the total inductance of the power inductor by an analytical method. The results obtained from the analytical model and finite element method exhibit good agreement with various design parameters and the error between the proposed model and measurement remains less than 7.91%, which indicates that the proposed model can predict the inductance suitably.

Keywords

• fully integrated inductor
• inductance model
• through-silicon vias (TSVs)
• mutual inductance
• 3D integration