An Energy-Efficient and High Throughput in-Memory Computing Bit-Cell With Excellent Robustness Under Process Variations for Binary Neural Network

Abstract

In-memory computing (IMC) is a promising approach for energy cost reduction due to data movement between memory and processor for running data-intensive deep learning applications on the computing systems. Together with Binary Neural Network (BNN), IMC provides a viable solution for running deep neural networks at the edge devices with stringent memory and energy constraints. In this paper, we propose a novel 10T bit-cell with a back-end-of-line (BEOL) metal-oxide-metal (MOM) capacitor laid on pitch for in-memory computing. Our IMC bit-cell, when arranged in a memory array, performs binary convolution (XNOR followed by Bit-count operations) and binary activation generation operations. We show, when binary layers of BNN are mapped into our IMC arrays for MNIST digit classification, 98.75% accuracy with energy efficiency of 2193 TOPS/W and throughput of 22857 GOPS can be obtained. We determine the memory array size considering the word-line and bit-line nonidealities and show how these impact classification accuracy. We analyze the impact of process variations on classification accuracy and show how word-line pulse tunability provided by our design can be used to improve the robustness of classification under process variations.

Keywords

• In-memory computing
• SRAM
• binary neural network
• nonideality
• process variation