Design, Simulation and Optimization of an Enhanced Vertical GaN Nanowire Transistor on Silicon Substrate for Power Electronic Applications

Abstract

A new vertical transistor structure based on GaN nanowire is designed and optimized using the TCAD-Santaurus tool with an electrothermal model. The studied structure with quasi-1D drift region is adapted to GaN nanowires synthesized with the bottom-up approach on a highly n-doped silicon substrate. The electrical performance is studied as a function of various epi-structure parameters, including region lengths and doping levels, nanowire diameter, and the impact of the surface states. The results reveal that the optimized structure has a Normally-OFF mode with a threshold voltage higher than 0.8 V and exhibits minimized leakage current, low on-state resistance, and maximized breakdown voltage. To the best of our knowledge, this is the first exhaustive study of GaN-based nanowire transistors, providing valuable insights for the scientific community and contributing to a deeper understanding of the impact of GaN nanowire parameters on device performance.

Keywords

• Normally-off
• vertical transistor
• GaN
• nanowire
• gate-all-around
• sentaurus TCAD