Low power true phase clock flip-flop based on the conditional precharge technique(基于条件预充电技术的低功耗真单相时钟触发器)

Abstract

Based on conditional precharge technology, a design method of high speed and low power real phase clock trigger is presented. This method controls the redundant precharge activity of internal nodes by adding field effectors and control conditions to the critical path with redundant switching activity. And by using the method of eliminating the redundant structure, it eliminates the redundant field effectors. This method improves the circuit structure and reduces the power dissipation and total power delay product. The simulation results of simulation program with integrated circuit emphasis, (HSPICE) show that the power dissipation of the proposed flip-flop is as low as 158.612 7 nW and the power delay product is as low as 0.048 735 fJ at 100 MHz operating frequency and low threshold voltage. The circuit has correct logic function and is superior to previous approaches in power dissipation and delay.(基于条件预充电技术，设计了一种高速低功耗真单相时钟触发器。在存在冗余开关活动的关键路径中，通过增加场效应管和控制条件，控制内部节点的冗余预充电活动；通过消除冗余结构，消除冗余的场效应管，从而改善电路结构，降低功耗和总功耗延时积。通用电路分析程序（simulation program with integrated circuit emphasis，HSPICE）仿真结果表明，在100 MHz的工作频率与低阈值电压下，触发器功耗低至158.612 7 nW、总功耗延时积低至0.048 735 fJ，电路具有正确的逻辑功能，且在功耗、延迟方面均优于近几年提出的电路。)

Keywords

• low power(低功耗)
• conditional precharge(条件预充电)
• near-threshold voltage(近阈值电压)
• true single phase clock(真单相时钟)