Ultra-Low Energy CNFET-Based Ternary Combinational Circuits Designs

Abstract

The embedded systems, IoT (Internet of Things) devices, and portable electronic devices spread very quickly recently. Most of them depend on batteries to operate. The target of this work is to decrease energy consumption by (1) using Multiple-valued logic (MVL) that shows notable enhancements regarding energy consumption over binary circuits and (2) using carbon nanotube field-effect transistors (CNFET) that show better performance than CMOS. This work proposes ternary combinational circuits using 32 nm CNFET: Ternary Half Adder (THA) with 36 transistors and Ternary Multiplier (TMUL) with 23 transistors. To reduce energy consumption by utilizing the unary operator of the ternary system and employing two voltage supplies ( $V_{dd}$ and $V_{dd}$ /2). The result of extensive HSPICE simulations regarding PVT (Process, Voltage, and Temperatures) variations and Noise Immunity Curve (NIC) show the improvements of the proposed designs up to 25% in transistors count and up to 98% in energy consumption reductions. Further, increasing the robustness of process variations and the noise tolerance compared to recent similar designs.

Keywords

• Noise immunity curve (NIC)
• CNTFET
• MVL
• PVT variations
• ternary logic circuits