Model-Based FPGA Implementation of a 6-DoF Dynamical Model Accelerator

Abstract

The mathematical model of 6-DoF dynamics is used in different applications. In general, software-based solutions are utilized to implement the 6-DoF dynamic model. This paper introduces the FPGA-based implementation of the 6-DoF dynamics accelerator. The proposed hardware-based approach ensures the accuracy of the nonlinear model without compromising computational speed. The model-based approach and high-level synthesis have been employed in the design and implementation stages. Regarding design strategy, standard processor architecture, and resource-sharing methods have been applied to achieve FPGA resource efficiency. Seven datapath and finite state machines have been designed for seven different subsystems. The design resulted in hardware blocks that can execute all non-linear model equations 396 times in 1 ms using fixed/floating-point hybrid case and 434 times using pure fixed-point case. The model equations, which took an average of $\mathbf {0.4986}$ s to simulate in the Simulink environment, have been run on an FPGA in $\mathbf {7.1924}~\mu \text{s}$ . For seven design cases, numerical errors, resource utilization, and timing metrics are tabulated and presented to the reader.

Keywords

• 6-DoF
• FPGA
• model-based design
• high-level synthesis
• dynamics
• quadrotor