Evaluating Ascon Hardware on 7-Series FPGA Devices

Abstract

The applications regarding the Internet of Things (IoT) demand lightweight and robust cryptographic solutions to ensure authenticated encryption with associated data (AEAD). Also, the lightweight cryptographic solutions that provide data confidentiality, integrity, and authenticity in a single algorithm are critical. In this regard, the CAESAR and NIST lightweight cryptography (LWC) competitions were concluded in 2019 and recently in 2023, respectively, with Ascon selected as the new LWC standard. Ascon has been evaluated (in the literature) for various characteristics, including some limited efforts on field-programmable gate array (FPGA) devices. A comprehensive evaluation of Ascon’s hardware implementation is still needed. Therefore, this work presents a unified hardware implementation of two variants of Ascon, i.e., Ascon-128 and Ascon-128a, to investigate the performance of the AEAD operation on 7-series FPGA devices up to the post-place and route level. For AEAD computations in our work, an iterative design-level approach with a finite-state machine (FSM)-based dedicated controller is employed. The benchmarking results show that Ascon utilizes 1632, 1497, 1904, and 1756 look-up tables on Virtex, Kintex, Spartan, and Artix 7-series FPGA devices, respectively. The operating frequencies on these devices are 335, 331, 309, and 317 MHz, with power consumptions of 239, 236, 219, and 222 mW. Consequently, our evaluation of Ascon demonstrates higher performance in operating frequency on Kintex-7 FPGA.

Keywords

• Ascon
• lightweight
• cryptography
• hardware
• accelerator
• architecture