A Highly Reliable Arbiter PUF With Improved Uniqueness in FPGA Implementation Using Bit-Self-Test

Abstract

Physically unclonable functions (PUFs) promise to be a critical hardware primitive for billions of Internet of Things (IoT) devices. The arbiter PUF (A-PUF) is one of the most well-known PUF circuits. However, its FPGA implementation has a poor reliability, and error correction codes (ECCs) are usually needed to eliminate the noise in the responses, which incur additional high hardware overhead and require NVM for helper data storage. In this paper, we present a highly reliable arbiter PUF with improved uniqueness using the bit-self-test (BST) strategy. A delay detection circuit is added into a classical arbiter PUF to test the delay deviation that produces each bit of the PUF response in real-time and mark the response as reliable using a reliability flag when the delay deviation is significantly more than a predefined threshold. Then, the robust responses can be used. We implemented the BST-arbiter PUF on a Xilinx Artix 7 FPGA. The test results show that the selected responses achieve outstanding performance where the bit error rate is less than 10-9, the bias is 50.3%, and the uniqueness is 49.1%. Thus, the BST-APUF, which drastically reduced the ECC overhead, can be applied to lightweight cryptography applications.

Keywords

• Physically unclonable functions
• bit-self-test
• arbiter PUF
• reliability enhancement
• reliability flag