Investigation of the influence of graded-gap layer formed by annealing on the electrical properties of the near-surface of LPE HgCdTe using MIS structure

Abstract

The influence of the near-surface graded-gap layer formed by annealing of HgCdTe grown by liquid phase epitaxy on the capacitance-voltage characteristics of its MIS structure was studied. We found that HgCdTe grown by LPE can form a near-surface graded-gap layer by annealing under specific conditions after CdTe passivation. After the near-surface graded-layer is generated, the performance of the HgCdTe surface layer has been changed significantly, showing as an increase of slow states, a decrease of fixed charge and the generation of single-level trap in the band gap. Furthermore, a Fermi level pinning phenomenon have been observed on the HgCdTe with graded-gap layer, highlighting the huge density of interface traps at the edge of the band. This effect may be attributed to the electric field generated by the graded-gap layer in HgCdTe driving minority carriers away from the interface. As a result, the surface recombination velocity of minority carriers is reduced. At the same time, it inhibits the oxidation reaction on the surface and consequently reduces the accumulation of fixed charges. During the annealing process to form the graded-layer, the defect system on the surface is reorganized, and the defect aggregation produces single-level defects and higher electron traps.

Keywords

• HgCdTe
• MIS structure
• annealing
• graded-gap layer
• capacitance–voltage characteristic