Zhejiang Daxue xuebao. Lixue ban (Jul 2001)

Logic design of priority encoder by restraining redundancy(抑制冗余优先编码器的逻辑设计)

LUYang-jian(卢仰坚),
WUXun-wei(吴训威)

Affiliations

LUYang-jian(卢仰坚): 1.Department of Information and Electronic Engineering, Zhejiang University, Hangzhou 310027, China( 1.浙江大学信息与电子工程学系，浙江　杭州　310027)
WUXun-wei(吴训威): 2. Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China( 2.宁波大学电路与系统研究所，浙江　宁波　315211)

DOI
Journal volume & issue: Vol. 28, no. 4
pp. 468 – 472

Abstract

基于低功耗设计的要求，对传统设计的优先编码器中的冗余现象加以研究，利用冗余抑制技术重构基于门级设计优先编码器电路结构.该优先编码器经PSPICE模拟验证具有正确的逻辑功能，并且被证明它能达到降低功耗的目的.

Published in Zhejiang Daxue xuebao. Lixue ban

ISSN: 1008-9497 (Print)
Publisher: Zhejiang University Press
Country of publisher: China
LCC subjects: Science: Mathematics: Instruments and machines: Electronic computers. Computer science; Science: Physics
Website: https://www.zjujournals.com/sci/EN/1008-9497/home.shtml

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