Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis

Abstract

In this paper, using calibrated TCAD simulations, we demonstrate how the performance of a Tunneling FET (TFET) can be improved by using a new phenomenon called drain induced barrier widening (DIBW) at the source-channel junction. Our results indicate that TFETs in which DIBW dominates exhibit a steep subthreshold swing (≈35 mV/dec) and a low OFF-state current ( $\approx 10^{-16}\text{A}/\mu \text{m}$ ) without affecting the ON-state current. We also show that TFETs exhibit a reverse short channel effect due to an increase in the tunneling width at the source-channel junction.

Keywords

• Drain induced barrier widening (DIBW)
• gate-on-drain overlap
• OFF-state current
• reverse short channel effects
• subthreshold swing
• TCAD simulation