A High Efficiency RF Power Amplifier Using Linearity-Enhanced Method in 40nm Standard CMOS Process

Abstract

A two-stage RF CMOS power amplifier with high linearity for WLAN is presented in this paper.The proposed PA consists of a programmable gain amplifier and a high power stage which is composed of a main amplifier with class AB bias and an auxiliary amplifier with class C bias. To improve the linearity ,an integrated diode linearition circuit provides a compensation mechanism for the input capacitance variation of the active devices,improving the linearity from the gain compressing. Moreover ,based on the un-even bias scheme,the power stage can improve linearity and reduce current consumption in the low power region. In order to demonstrate the feasibility of the technique,two types of PAs have been designed.The improved PA at 3.3V supply voltage,has a 37dB of power gain, 1.1 dBm increase of P,8.3% increase of PAE@Pand dB increase of ACPR for 802.11g WLAN,respectively,as compared with the traditional PA.