Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering

Abstract

As gate-all-around nanosheet transistors (GAA NSFETs) replacing current FinFETs for their superior gate control capabilities, it needs various performance optimizations for better transistor and circuit benefits. In this paper, special optimizations to source/drain (S/D) doping engineering including spacer bottom footing (SBF) and refining the lightly doped drain (LDD) implantation process are explored to enhance both fabricated complementary metal oxide semiconductor (CMOS) NSFETs and their 6T-SRAM cells. The experimental results demonstrate that the optimal SBF width increased the static noise margin (SNM) of the SRAM cells by 14.9%, while significantly reducing static power consumption for the balance performance between the NMOS and PMOS and reduced current in all leakage paths of SRAM. Moreover, the LDD optimization significantly reduced off-state leakage current ( $\rm I_{\mathrm {off}}$ ) for both NMOS and PMOS due to the reductions of peak electric field in overlap region between the S/D and the channel, leading to a 9.5% improvement in SNM and a substantial reduction in static power consumption. These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.

Keywords

• Gate-all-around nanosheet transistor (GAA NSFET)
• source/drain (S/D) doping
• spacer
• lightly doped drain (LDD)
• 6T static random-access memory (6T-SRAM)