Sub-10 nm Top Width Nanowire InGaAs Gate-All-Around MOSFETs With Improved Subthreshold Characteristics and Device Reliability

Abstract

In this article, sub-10 nm top width nanowire In0.53Ga0.47As gate-all-around (GAA) MOSFETs with improved subthreshold characteristics and reliability are demonstrated. These devices exhibit a significant improvement in the subthreshold performances with subthreshold swing (SS) of 70 mV/dec, drain induced barrier lowering (DIBL) of 46 mV/V, and off-current ( $\text{I}_{\mathrm{ off}}$ ) of $1.6 \times 10^{-4} \mu \text{A}/\mu \text{m}$ for InGaAs GAA MOSFETs. Effective control of short channel effects (SCEs) is confirmed by the error bar of statistical variation analysis. Under gate bias stress, a low degradation of SS and threshold voltage ( $\text{V}_{\mathrm{ th}}$ ) shift has been achieved due to N2 RP treatment of the InGaAs GAA MOSFETs. The superior performance can be attributed to the strong electrostatic control and high quality of high- $\kappa $ /InGaAs interface, originating from shrinking nanowire width and RP passivation effects. These results show the developed GAA MOSFET devices have good potential for future low-power high-switching speed CMOS logic applications.

Keywords

• Gate all around
• HfO₂
• SCEs
• RP treatment
• InGaAs
• MOSFET