IEEE Journal of the Electron Devices Society (Jan 2019)

Characterization of High-Performance InGaAs QW-MOSFETs With Reliable Bi-Layer HfO<sub>x</sub>N<sub>y</sub> Gate Stack

  • Su-Keun Eom,
  • Min-Woo Kong,
  • Ho-Young Cha,
  • Kwang-Seok Seo

DOI
https://doi.org/10.1109/JEDS.2019.2934745
Journal volume & issue
Vol. 7
pp. 908 – 913

Abstract

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In this work, we report high-performance InGaAs quantum-well MOSFETs with optimized bi-layer high-k gate dielectrics incorporating high-quality plasma-assisted atomic -layer-deposited (PA-ALD) HfOxNy interfacial layer (IL). With more than 1 nm IL deposition to passivate the InGaAs surface, excellent sub-threshold characteristics (SSmin = 68 mV/dec) were achieved through the proposed gate stack technology. We performed positive-bias-temperature-instability (PBTI) measure -ments in order to ensure a reliable gate operation. The proposed bi-layer III-V gate stack achieved the excellent value of maximum gate overdrive voltage (VOV, max) of 0.49 V with CET = 1.04 nm. The proposed gate stack has a great potential for III-V MOSFET technology to low power logic applications.

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