In-Line Tunnel Field Effect Transistor: Drive Current Improvement

Abstract

A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the subthreshold swing, and the intrinsic time delay, etc. The drive current of the in-line TFET is enhanced nearly 7× compared to the conventional TFET. It also shows a significantly reduced subthreshold swing of 37.2 mV/dec.

Keywords

• TFET
• in-line tunneling
• silicon
• vertical structure
• tunneling distance
• tunneling probability