IEEE Journal of the Electron Devices Society (Jan 2018)

A Multi-Bit Neuromorphic Weight Cell Using Ferroelectric FETs, suitable for SoC Integration

  • Borna Obradovic,
  • Titash Rakshit,
  • Ryan Hatcher,
  • Jorge Kittl,
  • Rwik Sengupta,
  • Joon Goo Hong,
  • Mark S. Rodder

DOI
https://doi.org/10.1109/JEDS.2018.2817628
Journal volume & issue
Vol. 6
pp. 438 – 448

Abstract

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A multi-bit digital weight cell for high-performance, inference-only non-GPU-like neuromorphic accelerators is presented. The cell is designed with simplicity of peripheral circuitry in mind. Non-volatile storage of weights which eliminates the need for DRAM access is based on FeFETs and is purely digital. The multiply-and-accumulate operation is performed using passive resistors, gated by FeFETs. The resulting weight cell offers a high degree of linearity and a large ON/OFF ratio. The key performance tradeoffs are investigated, and the device requirements are elucidated.

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