IEEE Journal of the Electron Devices Society (Jan 2021)

Understanding and Mitigating Stress Memorization Technique of Induced Layout Dependencies for NMOS HKMG Device

  • Ying-Fei Wang,
  • Qing-Chun Zhang,
  • Ping Li,
  • Xiao-Jing Su,
  • Li-Song Dong,
  • Rui Chen,
  • Li-Bin Zhang,
  • Tian-Yang Gai,
  • Ya-Juan Su,
  • Ya-Yi Wei,
  • Tian Chun Ye

DOI
https://doi.org/10.1109/JEDS.2020.3032957
Journal volume & issue
Vol. 9
pp. 6 – 9

Abstract

Read online

For the first time, this research addresses the notable layout proximity effects induced by stress memorization technique in planer high-k/Metal gate NMOS device systematically, including width effect, different shallow trench spacing effect, and length of diffusion effect. Based on the oxygen diffusion mechanism analysis of layout proximity effects in high-k/Metal gate NMOS device, an optimized process is proposed to suppress the layout dependency. The experiment result indicates that modified low temperature stress memorization technique process can suppress layout dependency efficiently without performance degradation of the devices.

Keywords