Design and Test of the In-Array Build-In Self-Test Scheme for the Embedded RRAM Array

Abstract

An in-array build-in self-test (BIST) scheme is proposed for the embedded resistive random access memory (RRAM) array. The BIST circuit consists of the linear-feedback-shift-register (LFSR)- based pattern generator and the multi-input signature register (MISR)-based response compactor, and both the n-stage LFSR and MISR are implemented by n + 2 in-array RRAM cells. The proposed LFSR/MISR circuit has better performance than the IMPLY-based counterpart, due to the application of the proposed three-cycle XOR gate and two-cycle shift gate with the in-array RRAM cells. And it is more area efficient comparing with the memristor ratioed logic (MRL)-based counterpart. The proposed n-stage LFSR/MISR circuit is tested by the scan chain method. The test method only has the linear time complexity. For the best of our knowledge, it is the first attempt to design the in-array BIST circuit for the RRAM array.

Keywords

• RRAM test
• LFSR
• MISR
• in-array BIST