Modeling of RRAM With Embedded Tunneling Barrier and Its Application in Logic in Memory

Abstract

This paper proposes a modeling technique for the evaluation of RRAM with embedded tunneling barrier that serves as an embedded selector, enabling high density integration while reducing the leakage current in a memory array. The further exploration of various biasing and pulsing schemes is provided so as to optimize programming efficiency for logic-in-memory application.

Keywords

• Resistive random access memory (RRAM)
• compact model
• selectorless RRAM
• logic in memory