A New Low Turn-Off Loss SOI Lateral Insulated Gate Bipolar Transistor With Buried Variation of Lateral Doping Layer

Abstract

In this paper, we propose a new low turn-off loss silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) with buried variation of lateral doping (VLD) layer. The proposed device features a VLD layer inserted in the drift region, which increases the doping dose (Q) and gradient (G) compared with Uniform P-buried (UPB) SOI LIGBT. The larger capacitance effect induced by lager Q and faster depletion leads to the lower rising anode voltage and reduced storage charge in the drift region. Therefore, a considerable low turn-off loss (Eoff) can be obtained. It is worth to note that owing to reshaped electric field in the new structure, the excess carriers of the drift region could be removed more quickly. Furthermore, larger G of the VLD layer improves the tradeoff between breakdown voltage and turn-off loss. The results of 2-D simulation indicate that the Eoff of the proposed device can reduce by 29.4% and 69.7% at 100 A $\cdot$ cm−2 and 200 A $\cdot$ cm−2, respectively, when compared with UPB SOI LIGBT

Keywords

• Variation of lateral doping (VLD)
• lateral insulated gate bipolar transistor (LIGBT)
• linear doping
• turn-off loss
• silicon-on-insulator (SOI)