Improving the Scalability of Ferroelectric FET Nonvolatile Memories With High-k Spacers

Abstract

This paper investigates scaled ferroelectric field-effect transistor (FeFET) nonvolatile memories (NVMs) with high-k spacer device design considering ferroelectric-dielectric random phase variations with TCAD atomistic simulations. Our study indicates that, in addition to raising the orthorhombic phase and reducing the grain size of the ferroelectric, using high-k spacers can serve as another way to enhance the scalability of FeFETs because it improves both the mean memory window (MW) and the worst-case MW. More importantly, these improvements increase with the down-scaling of gate length. In addition, we have investigated the impact of high-k spacers on the critical electric field across interfacial layer ( $\text{E}_{\mathrm{ IL}}$ ) for the reliability of FeFET NVMs. Our study suggests that, for scaled FeFETs with high-k spacers, the highest $\text{E}_{\mathrm{ IL}}$ during write operation is no longer located near the S/D edge but at the mid channel. Using high-k spacers can reduce the mid-channel $\text{E}_{\mathrm{ IL}}$ , and the reduction increases with decreasing gate length due to the increasing impact of high-k spacers. Our study may provide insights for future high-density FeFET design.

Keywords

• Ferroelectric field-effect transistor (FeFET)
• memory window (MW)
• nonvolatile memory (NVM)