Pattern-Centric Computational System for Logic and Memory Manufacturing and Process Technology Development

Abstract

Chip designers employ computer-aided design, circuit simulation, and design rule check systems. Lithography engineers employ model-based OPC (Optical Proximity Correction) and model-based print-simulation systems. Reticle inspection teams employ Aerial Image Measurement Systems® and Virtual Stepper® Systems. These teams are accustomed to evaluating and deploying state-of-the-art computational systems. When real-silicon fabrication begins, however, the teams responsible for line monitoring, wafer inspection, and yield attainment operate without the benefit of similarly advanced computational systems. In this paper we describe such a system and explore its applications and benefits. The system has received three U.S. patents [1,2,3] and brings together the significant potential of CAD (Computer Aided Design) layout (GDS, OASIS), Die-to-Database, and Machine Learning to build a dynamic, self-improving computational system. Featuring care area generation, advanced machine learning-based SEM (Scanning Electron Microscope) sampling that optimizes both DOI (Defect of Interest) capture rate and discovery of new defect types, comprehensive extraction of all Information of Interest(IOI) from all SEM images, detection of defect types not possible before, massive pattern fidelity analysis, full chip pattern decomposition and risk scoring via machine learning, innovative PWQ (Process Window Qualification) analysis and process window determination, risk assessment of new tape-outs, large scale in-wafer OPC verification and more, the system delivers a comprehensive pattern centric platform for process technology development and manufacturing.

Keywords

• die-to-database
• full chip decomposition
• machine learning
• defect discovery
• pattern fidelity
• pattern risk scoring
• opc verification
• process window qualification