A Simulation Study for Typical Design Rule Patterns in 5 nm Logic Process with EUV Photolithographic Process

Abstract

5 nm logic technology node is believed to be the first node that will adopt Extremely Ultra-Violet (EUV) lithography on a large scale. We have done a simulation study for typical 5 nm logic design rule patterns. In a 5 nm logic photo process, the most appropriate layers for the EUV lithography are the cut layers, metal layers, and via layers. Generally speaking, critical structures in a lithography process are semi-dense patterns, also known as the “forbidden pitch” patterns, the array edge structures, tip-to-tip structures, tip-to-line structures (under 2D design rules), the minimum area structures, the bi-lines, tri-lines, …, etc. Compared to that from the 193 nm immersion process, the behaviors for the above structures are different. For example, in the 193 nm immersion process, the minimum area is about 2~3 times that of minimum pixel squared, while in EUV photolithographic process, the minimum achievable area is found to be significantly larger. In the simulation, we have kept aware of the stochastics impact due to drastically reduced number of photons absorbed compared to the DUV process, the criteria used for various structures of image contrast are tightened. For example, in 193 nm immersion lithography, we have usually set the minimum Exposure Latitude (EL) for the poly layer, the metal layer, and tip-to-tip pattern, respectively, at 18%, 13%, and 10%. However, in EUV lithography, reasonable targets for the minima are, respectively, >18%, 18%, and 13%. We have also studied the aberration and shadowing impact to the above design rule structures. We will present the results of our work and our explanations.

Keywords

• 5nm design rule
• minimum area
• minimum exposure latitude
• aberration
• shadowing effect