An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

Abstract

This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance such as refresh time (tREF). However, no method is currently available for evaluating variations, which is a serious problem in developing DRAM. Although the average leakage current from a test element group has been used as an index for determining cell leakage, it does not provide the distribution of unit cell leakage current. We find that cell leakage distribution can be calculated from the slope of the retention time-fail bit plot (defined as TF slope). A steep slope indicates a narrow cell leakage distribution, which corresponds to a narrower structural distribution, and therefore a long tREF. Using statistical models and experiments based on extensive data, our results confirm this relationship. Another impact and contribution of TF slope are that the development period can be saved because a wrong decision (which process is better) can be avoided. This method is used successfully as an indicator to estimate selected processes and to facilitate DRAM development.

Keywords

• DRAM
• cell transistor
• leakage current distribution
• gate-induced drain leakage current (GIDL)
• process variation
• refresh time