The Chip-Level and Package-Level Degradation of Cascode GaN Device Under Repetitive Power Cycling Stress

Abstract

In this work, the electrical characteristics’ failure due to the chip-level damage and its relationship with the package-level degradation have been investigated for the Cascode GaN device under long-term repetitive power cycling test (PCT). At first, it is found that, the device’s transfer characteristics and threshold voltages have not changed until 8000-cycle PCT, while its on-state current decreases as the increases in cycles number. Meanwhile, the device’s gate-to-source leakage have not changed even after 8000-cycle PCT, but there is a significant increase in drain-to-source leakage. The above phenomenon has been attributed to the structural damage in the gate region of GaN HEMT, which has been verified by TCAD simulation and EMMI analysis. Then, it is found that the device’s thermal resistance is increased after the repetitive power cycling test, which is due to the package-level degradation. The increased thermal resistance will lead to the increase of heat accumulation, which has been verified by TCAD simulation, subsequently leading to the chip-level damage and electrical performance failure for Cascode GaN device. The relevant results may help to improve the long-term reliability of Cascode GaN device.

Keywords

• GaN HEMTs
• power cycling test
• package degradation
• chip-level degradation