IEEE Journal of the Electron Devices Society (Jan 2015)

Self-Rectifying Twin-Bit RRAM in 3-D Interweaved Cross-Point Array

  • Shu-En Chen,
  • Yung-Wen Chin,
  • Min-Che Hsieh,
  • Chu-Feng Liao,
  • Tzong-Sheng Chang,
  • Chrong-Jung Lin,
  • Ya-Chin King

DOI
https://doi.org/10.1109/JEDS.2015.2425652
Journal volume & issue
Vol. 3, no. 4
pp. 336 – 340

Abstract

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A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaOxN RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.