Analysis of High-Temperature Data Retention in 3D Floating-Gate nand Flash Memory Arrays

Abstract

In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms give rise to threshold-voltage $(\mathbf {V_{T}})$ instabilities with similar activation energy and comparable magnitude on fresh devices. On the other hand, polysilicon trap depassivation displays a negligible strengthening with cycling and a more marked dependence on the cell $\mathbf {V_{T}}$ level during data retention with respect to charge detrapping. Results must be carefully considered in the reliability assessment of all state-of-the-art and future 3D NAND Flash technology nodes.

Keywords

• NAND Flash memory
• 3D array
• polysilicon
• semiconductor device reliability
• semiconductor device modeling