Low-Power Vertical Tunnel Field-Effect Transistor Ternary Inverter

Abstract

In this study, vertical tunnel FET-based ternary CMOS (T-CMOS) is introduced and its electrical characteristics are investigated using TCAD device and mixed-mode simulations with experimentally calibrated tunneling parameters. This new T-CMOS utilizes two different types of tunneling currents to form three different output voltage states: (1) source-to-drain tunneling current; and (2) conventional source-to-channel tunneling current. To form a half supply voltage ( $\text{V}_{DD}$ ) output voltage during the inverter operation, the n-/p-type devices of the proposed T-CMOS are designed to have constant source-to-drain tunneling current regardless of gate voltage ( $\text{V}_{GS}$ ) by using nitride spacer between gate and drain. Also, typical binary inverter operation is performed using the source-to-channel tunneling. In voltage transfer characteristics (VTC), it is confirmed that there is the clear half $\text{V}_{DD}$ state after matching the tunneling currents of the n-/p-type devices. It is revealed that the stable half $\text{V}_{DD}$ state cannot be achievable if the currents are mismatched by gate workfunction, gate dielectric thickness, and interface trap variations, implying that the current matching between n-/p-type devices is crucial to obtain stable ternary operations.

Keywords

• Band-to-band tunneling (BTBT)
• vertical tunnel field-effect transistor (vertical tunnel FET)
• ternary inverter
• subthreshold swing (SS)
• ternary CMOS (T-CMOS)
• line tunneling