TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization

Abstract

Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of $G_{2}$ significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.

Keywords

• Vertical transistor
• double-surrounding-gate
• TCAD
• a-IGZO
• gate length
• gate position