A Novel Multi-Scale Method for Thermo-Mechanical Simulation of Power Integrated Circuits

Abstract

During development of power Integrated Circuits (IC), several iterations between the design and test/ measurement steps are performed. Computer-aided engineering significantly shortens the product development process because the numerical simulations can identify and remediate most deficiencies during the design stage. The recent IC manufacturing technologies lead to ca. $10^{4}$ -order scale separation between transistor cell details and the device active area, resulting in very complex IC models. For the IC complexity to be overcome, advanced multi-scale analysis methods are required to perform accurate simulations in a decent time (order of hours). This paper proposes an advanced and enhanced multi-scale simulation method for the thermo-mechanical analysis of power ICs. The computational IC structure is automatically generated from a Cadence layout and partitioned into far-field and homogenized regions - the macro-model. Detailed localized micro-scale sub-models are assigned to limited portions of the homogenized region. The two-way simulated data transfer between the homogenized macro-model and the micro sub-models is one multi-scale approach novelty proposed in this paper. The method is validated on a real test chip structure presented in literature. The proposed multi-scale approach in conjunction with the two-way macro-micro data transfer lead to similar accuracy in the prediction of defect location, yet with significant simulation time - and computational resource reduction (CPU time and RAM usage reduced by almost 80% and 60% respectively) compared to the method used as reference.

Keywords

• Reliability simulation
• DMOS structure
• multi-level simulation method
• sub modeling
• fast thermal cycling
• power cycling