On the Nature of the Memory Mechanism of Gated-Thyristor Dynamic-RAM Cells

Abstract

With the help of numerical simulations, we revisit the operation of dynamic thin-capacitively-coupled-thyristor RAM (TRAM) and field effect diode-RAM cells and clarify the memory mechanism. The resulting carrier profiles demonstrate that the recently advanced interpretation of the physical memory (i.e., store) mechanism, as the accumulation (“1”) or depletion (“0”) of holes in the p-base (under the gate), is incorrect. Instead, it turns out that it is the presence (“0”) or absence (“1”) of deeply depleted regions within the TRAM structure, associated with the two p-n junctions on the sides of the p-base that determines the stored state of the cell.

Keywords

• TRAM
• FED-RAM
• TCCT
• FED
• FBC
• SOI