Comparison of Two in Pixel Source Follower Schemes for Deep Subelectron Noise CMOS Image Sensors

Abstract

This paper compares two in-pixel source follower stage designs for low noise CMOS image sensors embedded both on a same 5 mm by 5 mm chip fabricated in a 180nm CIS process. The presented chip embeds two pixel variants, one based on a body-effect-canceled thin oxide PMOS and the other embeds a native thick oxide NMOS. On the other hand they share the same sense node, same amplification circuit and 11bit single slope analog to digital converter (SS-ADC). The imager characterization demonstrates a histogram peak noise of 0.34e $^{-}_{\text{RMS}}$ with the PMOS SF pixel and 0.47e $^{-}_{\text{RMS}}$ with the NMOS SF at maximum analog gain. This performance is obtained at room temperature and 119 frame per second. Both pixel variants demonstrate a full well capacity over 5600 electrons.

Keywords

• CMOS
• 4T
• CIS
• conversion gain
• sub-electron noise
• wide dynamic