Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

Li Lu; Feng Lin; Shulang Ma; Zhibo Yin; Yuanchang Sang; Weifeng Sun; Siyang Liu; Wei Su

doi:10.1109/JEDS.2021.3128755

IEEE Journal of the Electron Devices Society (Jan 2021)

Hot-Carrier-Induced Reliability for Lateral DMOS Transistors With Split-STI Structures

Li Lu,
Feng Lin,
Shulang Ma,
Zhibo Yin,
Yuanchang Sang,
Weifeng Sun,
Siyang Liu,
Wei Su

Affiliations

Li Lu: National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Feng Lin: National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Shulang Ma: Process Integration Technology Research Center, CSMC Technologies Corporation, Wuxi, China
Zhibo Yin: National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Yuanchang Sang: National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Weifeng Sun: ORCiD; National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Siyang Liu: ORCiD; National ASIC System Engineering Research Center, School of Electronic Science and Engineering, Southeast University, Nanjing, China
Wei Su: Process Integration Technology Research Center, CSMC Technologies Corporation, Wuxi, China

DOI: https://doi.org/10.1109/JEDS.2021.3128755
Journal volume & issue: Vol. 9
pp. 1188 – 1193

Abstract

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In this work, four kinds of lateral double-diffused MOS (LDMOS) devices with different split shallow trench isolation (STI) structures (Device A: LDMOS with traditional split-STI, Device B: LDMOS with slope-STI, Device C with step-STI and Device D with H-shape-STI) have been fabricated and the hot-carrier reliabilities also have been investigated due to the serious environment they are endured. The maximum bulk current (Ibmax) stress and the maximum gate voltage (Vgmax) stress have been carried out and the inner mechanism of device degradation have been investigated successfully. With the assistance of the T-CAD simulation tools, it is found that the main damage point locates at the STI conners with a mount of interface states generation, inducing serious degradation for these four devices. The Device D owns high hot-carrier reliability due to its special structure with narrow split-STI. The worst device is Device C because of the presence of extra STI damage point. Finally, a mechanism verification, the charge pumping (CP) method has been applied to better understand this work.

Published in IEEE Journal of the Electron Devices Society

ISSN: 2168-6734 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245494

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