Sputter-Deposited-MoS2 <inline-formula> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula>MISFETs With Top-Gate and Al2O3 Passivation Under Low Thermal Budget for Large Area Integration

Kentaro Matsuura; Jun'Ichi Shimizu; Mayato Toyama; Takumi Ohashi; Iriya Muneta; Seiya Ishihara; Kuniyuki Kakushima; Kazuo Tsutsui; Atsushi Ogura; Hitoshi Wakabayashi

doi:10.1109/JEDS.2018.2883133

IEEE Journal of the Electron Devices Society (Jan 2018)

Sputter-Deposited-MoS2 <inline-formula> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula>MISFETs With Top-Gate and Al2O3 Passivation Under Low Thermal Budget for Large Area Integration

Kentaro Matsuura,
Jun'Ichi Shimizu,
Mayato Toyama,
Takumi Ohashi,
Iriya Muneta,
Seiya Ishihara,
Kuniyuki Kakushima,
Kazuo Tsutsui,
Atsushi Ogura,
Hitoshi Wakabayashi

Affiliations

Kentaro Matsuura: ORCiD; Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Jun'Ichi Shimizu: ORCiD; Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Mayato Toyama: Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Takumi Ohashi: Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Iriya Muneta: ORCiD; Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Seiya Ishihara: School of Science and Technology, Meiji University, Kawasaki, Japan
Kuniyuki Kakushima: Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Kazuo Tsutsui: ORCiD; Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan
Atsushi Ogura: School of Science and Technology, Meiji University, Kawasaki, Japan
Hitoshi Wakabayashi: ORCiD; Department of Electrical and Electronic Engineering, School of Engineering, Tokyo Institute of Technology, Yokohama, Japan

DOI: https://doi.org/10.1109/JEDS.2018.2883133
Journal volume & issue: Vol. 6
pp. 1246 – 1252

Abstract

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We have fabricated large area integrated top-gate ${n}$ MISFETs with sputter-deposited-MoS2 film having n-type operation. A sputtering method enables us to form a large-area MoS2 thin film followed by H2S annealing to compensate sulfur vacancies. Two passivation films of ALD-Al2O3 enhance the process endurance of MoS2 channel. Therefore, we demonstrate TiN-top-gate ${n}$ MISFET, which is a substantial first step to realize industrial chip-level LSIs with MoS2-channel FETs.

Published in IEEE Journal of the Electron Devices Society

ISSN: 2168-6734 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6245494

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