IEEE Journal of the Electron Devices Society (Jan 2021)

Investigation of Re-Program Scheme in Charge Trap-Based 3D NAND Flash Memory

  • Ting Cheng,
  • Jianquan Jia,
  • Lei Jin,
  • Xinlei Jia,
  • Shiyu Xia,
  • Jianwei Lu,
  • Kaiwei Li,
  • Zhe Luo,
  • Da Li,
  • Hongtao Liu,
  • Qiguang Wang,
  • An Zhang,
  • Daohong Yang,
  • Zongliang Huo

DOI
https://doi.org/10.1109/JEDS.2021.3081635
Journal volume & issue
Vol. 9
pp. 640 – 644

Abstract

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Early retention or initial threshold voltage shift (IVS) is one of the key reliability challenges in charge trapping memory (CTM) based 3D NAND flash. Re-program scheme was introduced in quad-level-cell (QLC) NAND (Shibata et al., 2007, Lee et al., 2018, Shibata et al., 2019, and Khakifirooz et al., 2021), and the IVS improvement by re-program scheme was reported. In this work, it is found that re-program can suppress ~81% of IVS in 3D NAND, which is much more significant than that of 2D NAND ~50% (Chen et al., 2010). The mechanisms of IVS improvement by re-program scheme in 3D NAND are investigated. Both vertical de-trapping in the BE-tunneling oxide and charge lateral migration (LM) in the charge-trap layer are suppressed in re-program. Re-program is effective in vertical de-trapping suppression both in checker-board pattern (C/P) and solid-board pattern (S/P) cases, and is effective in LM suppression only in C/P case. Furthermore, the LM improvement by re-program scheme is more pronounced with gate length (Lg) and inter-gate space (Ls) scaling down, showing potential in the reliability improvement of advanced 3D NAND technologies.

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