Fabrication and Characterization of a Novel Si Line Tunneling TFET With High Drive Current

Abstract

In this paper, an N-type silicon line tunneling TFET (LT-TFET) with an ultra-shallow N+ pocket was proposed. The pocket was formed by using the germanium preamorphization implantation (Ge PAI), arsenic ultra-low energy implantation and spike annealing. Due to the Ge PAI, the tunneling probability was improved significantly. As a result, a high on-state current of 40 μA/μm, a minimum subthreshold swing (SS) of 69 mV/decade and an average SS of 80 mV/decade over 5 decades of drain current were achieved with VDS = VGS = 1 V at room temperature. It is shown that once the trap assisted tunneling is suppressed at the low temperature, the band-to-band tunneling becomes dominant. When the temperature decreases from 300 K to 4.9 K, the on-state current only reduces 20% and a minimumpoint SS of 10 mV/decade was obtained. The LT-TFET exhibits improved transconductance efficiency at deep cryogenic temperature range. The proposed structure in this work shows attractive merits in the cryogenic digital and analog application.

Keywords

• TFET Ge PAI
• line tunneling
• cryogenic temperature