Investigation of the DC Performance and Linearity of InAlN/GaN HFETs via Studying the Impact of the Scaling of L_GS and L_G on the Source Access Resistance

Abstract

In this manuscript, we have investigated the impact of the scaling of the gate-source length (LGS) and gate length (LG) on the output characterises and gate-transconductance (Gm) linearity of metallic-face InAlN/AlN/GaN heterostructure field effect transistors (HFETs) having fin structures only under the gate and those having them stretched from source to drain. Evidence for both device types suggests that the downscaling of LGS and LG augments the electron velocity in the source-access region, as a result of which the higher carrier density under the gated-channel improves the maximum drain-current density but not necessarily the $G_{m}$ linearity of the device. It is shown that the devices having a planar and longer source access region are exhibiting relatively improved gate-transconductance linearity. This is suggested to be due to their almost constant source access resistance (Rs). In addition, the downscaling of the LG is observed to have a positive influence on device linearity. This observation could be due to the larger exposure to the drain-induced barrier lowering (DIBL) and the resulting rush of the carriers from the source access region to the gated-channel, leading to the suppression of the increasing $R_{s}$ at higher drain currents.

Keywords

• InAlN/GaN
• heterostructure field effect transistor (HFET)
• lattice-matched
• source access resistance
• transconductance linearity