Relaxation of Self-Heating-Effect for Stacked-Nanowire FET and p/n-Stacked 6T-SRAM Layout

Abstract

In this paper, we investigated the source/drain recessed contact structure to mitigate the self-heating-effects in vertically stacked-nanowire FETs. As a result, lattice temperature of nanowire regions during device operation was considerably decreased by using the source/drain recessed contact structure. This is attributed to an increase in heat dissipation mainly from heat source to bulk wafer. Moreover, we proposed the p/n-stacked nanowire on bulk FinFET and its 6T-SRAM layout. Area of the proposed SRAM was reduced approximately 15%, as compared to the conventional cell layout.

Keywords

• Vertically-stacked nanowire FETs
• accumulation mode operation
• self-heating-effect
• source/drain recessed contact
• p/n-stacked nanowire on bulk-FinFET%22%2C%22default_operator%22%3A%22AND%22%7D%7D%7D"> <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">p/n</italic>-stacked nanowire on bulk-FinFET
• 3-dimensinal 6T-SRAM layout