IEEE Journal of the Electron Devices Society (Jan 2024)
A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design
- Hao Su,
- Yiyuan Cai,
- Shenghua Zhou,
- Guangchong Hu,
- Yu He,
- Yunfeng Xie,
- Yuhuan Lin,
- Chunhui Li,
- Tianqi Zhao,
- Jun Lan,
- Wenhui Wang,
- Wenxin Li,
- Feichi Zhou,
- Xiaoguang Liu,
- Longyang Lin,
- Yida Li,
- Hongyu Yu,
- Kai Chen
Affiliations
- Hao Su
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Yiyuan Cai
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Shenghua Zhou
- Shenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, China
- Guangchong Hu
- Integrated Circuits and Electronics Center, International Quantum Academy, Shenzhen, China
- Yu He
- Shenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, China
- Yunfeng Xie
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Yuhuan Lin
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Chunhui Li
- Shenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, China
- Tianqi Zhao
- Shenzhen Institute for Quantum Science and Engineering, Southern University of Science and Technology, Shenzhen, China
- Jun Lan
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Wenhui Wang
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Wenxin Li
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Feichi Zhou
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Xiaoguang Liu
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Longyang Lin
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Yida Li
- ORCiD
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Hongyu Yu
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- Kai Chen
- School of Microelectronics, Southern University of Science and Technology, Shenzhen, China
- DOI
- https://doi.org/10.1109/JEDS.2024.3359664
- Journal volume & issue
-
Vol. 12
pp. 859 – 867
Abstract
This paper proposes a physical charge-based analytical MOSFET threshold voltage model that explicitly incorporates interface-trapped charges which have been identified as playing a dominant role in defining threshold voltage trends in deep cryogenic temperatures. The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. Excellent fit between the model and measurement data from 180-nm bulk foundry devices is shown from room temperature to 4 K.
Keywords
