Generating Predictive Models for Emerging Semiconductor Devices

Abstract

Circuit design requires fast and scalable models which are compatible to modern electronic design automation tools. For this task typically analytical compact models are preferred. However, for emerging device concepts with altered conduction mechanisms like reconfigurable FETs, tunnel FETs or feedback FETs compact models are often not yet ready for circuit simulation environments. Table models help to bridge this gap, as they only require biasing values in form of current- and capacitance tables, which are then interpolated during circuit simulation. However, the conventional approach of generating the data set through DC ramps in physical simulation typically results in a large number of TCAD simulations and many redundant data points. To simplify model building, cut turnaround time and omit redundant data, this work proposes to restrict to a single transient TCAD simulation, where all required bias points for a fully functional predictive table model are provided by nesting harmonic functions. The mathematical reasoning for the selection of appropriate parameters such as frequencies and sampling rate are presented and their influence on the quality of the obtained table model is exposed. This work further presents implementation of the modeling method including validation and post-processing of the transient simulation result. The target device is an emerging reconfigurable FET (RFET) with planar structure. Finally, the performance of the obtained predictive table model of the RFET is demonstrated with circuit simulation of logic cells.

Keywords

• Semiconductor device modeling
• circuit simulation