IEEE Journal of the Electron Devices Society (Jan 2015)

Best Practices for Compact Modeling in Verilog-A

  • Colin C. McAndrew,
  • Geoffrey J. Coram,
  • Kiran K. Gullapalli,
  • J. Robert Jones,
  • Laurence W. Nagel,
  • Ananda S. Roy,
  • Jaijeet Roychowdhury,
  • Andries J. Scholten,
  • Geert D. J. Smit,
  • Xufeng Wang,
  • Sadayuki Yoshitomi

DOI
https://doi.org/10.1109/JEDS.2015.2455342
Journal volume & issue
Vol. 3, no. 5
pp. 383 – 396

Abstract

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Verilog-A is the de facto standard language that the semiconductor industry uses to define compact models. Unfortunately, it is easy to write models poorly in Verilog-A, and this can lead to unphysical model behavior, poor convergence, and difficulty in understanding and maintaining model codes. This paper details best practices for writing compact models in Verilog-A, to try to help raise the quality of compact modeling throughout the industry.