Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

Abstract

Significant impact of the ion-implant straggle of the P+ shielding region on the static and dynamic characteristics of 1.2 kV 4H-SiC power MOSFETs is demonstrated in this paper by using analytical and TCAD modeling. The P+ region ion-implant straggle not only reduces the JFET width but increases the channel length. This combination is shown to displace a SiC power MOSFET structure optimized without ion-implant straggle away from the optimum JFET width required to achieve the lowest specific on-resistance, resulting in an increase in the specific on-resistance by a factor of 2-3x for the typically used JFET width of $0.7 \mu \text{m}$ . The theoretical analysis is supported by data measured on 1.2 kV SiC power MOSFETs fabricated with channel lengths of 0.3 and $0.5 \mu \text{m}$ using both accumulation and inversion mode channels. The presence of the P+ shielding region ion-implant straggle is shown to: (a) increase specific on-resistance by 15-30%; (b) suppress short-channel effects; (c) reduce electric field in the gate oxide; (d) reduce the transconductance; (e) reduce saturated drain current; and (f) significantly reduce the gate-drain capacitance and gate charge. Impact of P+ shielding region lateral straggle on device cell optimization is an important contribution of this paper.

Keywords

• 4H-SiC
• accumulation
• capacitance
• cell optimization
• gate charge
• inversion